The following Quickstart Guide will show new users how to create, edit, simulate, and compile a circuit for Xilinx Foundation using schematic capture. "Schematic capture" simply refers to a program capable of reading and working with schematics drawn into the computer. There are two other forms of circuit entry possible with Xilinx Foundation: HDLs (Hardware Description Languages, such as VHDL and Abel) and the State Editor. These are currently not discussed in this tutorial, but later it may be expanded to include these topics.
Please send corrections to tsaimelv@pilot.msu.edu.
Start the program by going to the "Xilinx Foundation Project Manager" icon in
the Start menu. There are many other icons in the menu that you can click
on, including an extensive array of online documentation. It is
recommended that you read the documentation included with Xilinx Foundation in
addition to this tutorial.
Once started, you will see the main design window. We want to create a
new project for this tutorial, so click on "New Project":
The "New Project" window will show up. Type in the name you want to call the project, as well as the specified directory. You cannot create a project in the default directory that first comes up, so specify C:\TEMP or point it to somewhere in your M:\ drive. The name of the project will actually become the name of the subdirectory containing your project. For example, the files contained in the above project will be put into E:\TEMP\intro.
Next you must specify the "Family" and "Part". When creating designs
with Xilinx Foundation, the program must know what type of chip you are dealing
with. In EE 411, we deal with two different chips: the XC95108 (the
CPLD chip contained in the XS95 board) and the XC4010XL (the FPGA contained in
the XS40 board). Depending on which chip you select, it can make drastic
differences in how you enter schematic-based designs. However, for this
tutorial, it doesn't matter what family or part you choose, any will do.
But you might as well get used to entering in the correct part #. The
"Speed" box determines how fast our chip is capable of running, but for this
class it will have little or no bearing on your projects.
Once you have created your project, there will be many files created within the project directory you specified. The most important ones show up in the left pane of the window. The "INTRO.UCF" file is the Universal Constraint File for your project. Editing this file allows you to change a number of different preferences and options for your project. Consult the online help or your Xilinx Student Edition book for more information on the UCF file. For now we will ignore this and the other files contained within the project directory.
Since this tutorial shows how to enter a circuit using schematic capture, we
must first create a blank schematic sheet. Do this by clicking on the
"Schematic Editor" button in the design flow window.
Once the blank schematic sheet has been created, we can now start adding
elements of our circuit. Do this by clicking on the Symbols Toolbox
button.
First we want to add a 2-input "AND" gate to our circuit. Scroll down
the symbol toolbox and find AND2. This is a 2-input AND gate.
Click on its name once, then move the mouse pointer into a blank area of the
schematic. Click once more and the gate will be placed into the schematic
sheet. Take a while to get a feel for how to add, move, select, and delete
schematic symbols as they're placed onto the sheet. It can be tricky.
Now we want to add a 2-input OR gate to our circuit. Just as before,
find the OR2 entry and add it.
And finally we shall add an inverter. In order for this circuit to
function, we obviously must add wires to interconnect the components.
However, we will wait until the end to do this to make things easier.
Remember that the ultimate goal of this schematic is to have it be synthesized down to an FPGA. That is, the circuit that we draw will exactly be implemented inside the FPGA or CPLD. In order for the program to properly recognize how we want this to be done, we must add "input buffers" and "output buffers." These buffers tell Foundation where we want physical inputs and outputs to be oriented on the FPGA. If this is confusing, don't worry, all you have to know is that these components must be added. Understanding their function is unimportant at this time.
Scroll down and find IBUF just as any other component. We will
have three inputs and one output, so we must add three IBUFs.
For our output we must add an OBUF.
After we have added the IBUF's and OBUF's that define where we want inputs and outputs, we must then add "pin identifiers." These allow us to name the IBUF and OBUF pins. Once we add the input and output terminal identifiers, we can then use these as "pin names" during simulation of the circuit.
To add an Input Terminal, click on the button in the upper left of the "SC Symbols" window. The "I/O Terminal" window will then appear. We'll call our first pin A, so type this into the Terminal Name input box. Click OK and then place the symbol just as any other component.
Notice how the I/O terminal "A" is a different color than the other symbols. Place it near the first IBUF. Again, we'll connect wires later.
Proceed to add two more Input Terminals, "B" and "C." Place them under the first terminal "A."
Since we have an output pin, our final I/O terminal must be an output. Name it "D."
After all the components have been added, this is what it should look like. Notice the difference in appearance between the Input and Output terminals.
All components have been placed, so now we need to connect them with wires. Do this by clicking on the "Draw Wires" button.
To draw wires between components, right-click once, move the mouse pointer, then right click again to end the wire. Just as in placing components, adding and editing wires can be tricky so get experiment with wire placement. If a wire has not been properly placed, it will automatically erase itself after you try to do something else. It is difficult (but not impossible) to screw up placement of wires. It gets especially tricky when dealing with busses, but we won't be adding busses at this point.
Here is the schematic with a few more wires to go...
Here is the completed schematic. Wasn't that easy!?
Now you should save the schematic. When you click "save," the schematic
file will be automatically added to the project directory. It is possible
to have multiple schematics within a single project.
Each component has certain properties associated with it. For example, if we wanted to specify the actual pin number (on the physical FPGA chip) that we want our schematic terminals to correspond to, you can edit the IBUF and OBUF properties by double clicking on the symbol.
If we wanted terminal "A" to be placed on pin 47 of our CPLD chip, we add the parameter "LOC" (location) and its description p47 (pin 47). Clicking "Add" will incorporate this pin # into the schematic. When the final project is completed and synthesized, this IBUF will actually be placed on the corresponding FPGA pin. You can also specify pin #'s from within the UCF file. Nonetheless, we don't have to specify the pin number for this example, go ahead a click "Cancel."
We must now create the netlist for our schematic.
When Foundation creates the netlist, it creates a file that contains a low-level
description of our file, consisting of primitive components connected
together. It is very similar to a pspice .cir file.
After it creates the netlist, it gives you some warnings, see below:
The warning says "terminals for top level schematic." This warning was generated for a specific reason... Foundation and most other EDA software packages now focus on modular and hierarchical design. The schematic that we just drew, for example, could be put into it's own "component" symbol and then used within another schematic in a nice-and-neat fashion. However, we want this schematic to be implemented directly within the FPGA and will not be used as a module in another design, so it gave us this warning. For now we can ignore it.
After the netlist was created, we perform an integrity test. This tests the netlist to see if it obeys certain design rules that it must follow.
The test passed, our design doesn't break any design rules.
After the netlist was created and tested, it must now be "exported" for use in the main design.
We want to select the Edif 200 format (*.EDN) for exporting. The other formats are used in other cases.
You don't need to change the filename or extension (intro.alb). Xilinx handles this, simply click "open" after you've selected Edif 200 format.
After all that, you can now close the schematic editor and go back to the project manager. We now want to see if our schematic actually works. This is done by simulation of the circuit, click on "SIM Funct."
This is the simulation environment provided by Foundation. Right now we'll only be performing a static timing analysis. That is, we're assuming that the gates and wires that we created from within the schematic are infinitely fast. This simulator will not take into account real-world gate delays, capacitance, etc. that could alter real-world simulation results. Only after the design has been compiled and synthesized can the simulator account for such delays. In any case, our circuit is so simple that we can effectively ignore any delays in the circuit.
We must first specify what parts of our circuit we want the simulator to monitor. Click on "Add Signals."
In this window we must select the signals we want the simulator to deal with. These signals are contained within the "Signals Selection" pane. We can ignore the "Chip Selection" and "Scan Hierarchy" panes right now.
In the Signals Selection pane, you see the four I/O terminals that we added within our schematic, A, B, C, and D. Click on "A" and then click "Add".
A red checkmark indicates that it has been added into the simulator. Proceed to add the other three terminals.
All four terminals have been added, inputs A, B, and C, as well as output D. Click on "close" to go back to the simulator window.
Note that the four signals are now placed in the simulator window.
Since A, B, and C are inputs, we must add some sort of driving signals so that we can test to see if our output 'D' is actually working properly (hence the reason we perform simulation). We will first add a driver to signal "A". Click on signal "A" and it will be highlighted with a blue shadow.
Click on "Add Stimulators" after A has been highlighted.
The "Stimulator Selection" window will then come up. This window is a bit confusing, and I recommend that you eventually read the Xilinx online documentation on how to use all the features of the Stimulator Selection window.
The row of "lights" after the Bc: each correspond to a different bit in a 16-bit binary counter (Bc stands for binary counter). In this fashion, we can make any input be driven by a bit in this counter. Click on the least significant bit of Bc: (where the mouse is pointing) to make A become part of this 16 bit counter. If you are confused about this, don't worry, you'll see what this does in a moment.
After this button is clicked, notice how A gets a "B0" placed after it in the simulator window.
Proceed to do the same for B and C, but use the next two digits of the counter. For example, the mouse pointer is the button you should click for signal C. B gets a "B1" after it and C gets a "B2."
We to do a functional (static) simulation, so make sure "Functional" is highlighted.
We can now finally perform the simulation. Click the "Long Step" button to have the simulator run for 200 nanoseconds. If you want you can change the value of how long it simulates when performing a "long step."
The following results should show up. If the waveforms are all scrunched together or you can't see anything but a short dark line behind A, B, and C, then your window scale is miscalibrated. See the next image:
To "compress" the waveform so that more fits on the screen, click on the button that looks like an upside-down rake (where the mouse pointer is). To widen the waveform view, click on the other button (to the right of "500ps/div"). Widening the screen may be necessary in order to view any of the simulation, it depends on the default value the simulator opens with.
After you get the waveform to a scale you desire, you can now see what is going on. Notice how signal "A" cycles twice for every one time B does, and B cycles twice every one time C does. This is because the stimulator was part of a binary counter, and C was the MSB and A was the LSB of this counter.
Since this was a combinational circuit, we wanted to test every possible
input combination, and using bits of a counter was the easiest way. We can
now produce a truth table based on the simulation results:
| A | B | C | D |
| 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 |
| 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 1 |
| 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 1 | 1 | 1 |
Now that we have verified that the circuit works, you can exit the simulator window. We must now synthesize the circuit into a format that we can download to the FPGA board. To do this, click on "Implement" in the design flow window.
This starts the Design Manager. Design Manager serves a number of different functions, but we won't go into that right now.
To begin synthesis click on "implement" in the menu bar.
This brings up the implementation window. From here you can specify various options, revision and version names, etc for use in synthesis. To start synthesis, click on "Run." However, at this early stage, the process of synthesis will not be discussed. Consult the online documentation or your Xilinx Student Edition book for more information.