In the first Xilinx Quickstart Guide, you learned how to create, edit, and simulate schematic designs using Xilinx Foundation.  However, the ultimate goal of this process is to create a bitstream that can be downloaded to an FPGA or CPLD.  As you know, this bitstream will internally configure the FPGA or CPLD chip to perform whatever hardware function you created from within Foundation.  This tutorial demonstrates the process of creating a hardware design from within Foundation, synthesizing the design, downloading the synthesized bitstream to an FPGA board (the XS40 board from XESS corporation), and testing the completed circuit.

Please send comments/corrections to tsaimelv@pilot.msu.edu.

An Introduction to the XS40 FPGA Board

XESS Corporation has many products based around FPGAs and CPLDs.  Our ECE department has obtained a number of the XS40 and XS95 fpga/cpld development boards, and these are what students in EE 411 will be using.

This tutorial applies mainly to the XS40 board, although most information also applies to the XS95 board.  See the end of this tutorial for information specific to the XS95 board.  The XS40 is a small development board containing a Xilinx XC4010XL series FPGA chip.  This chip is a low to midrange size FPGA in comparison to other FPGAs that Xilinx manufacturers.  Nonetheless, it is unlikely that you will "fill up" the entire FPGA with the designs in EE 411.  The XC4010XL contains 400 "Configurable Logic Blocks" (CLBs), which corresponds to around 7000 to 20000 "usable gates."  This means that when creating a real-world hardware design, the XC4010XL chip can implement a circuit that is equivalent to 7000 to 20000 two-input NAND gates (as you recall, any digital circuit can be broken down into a series of NAND or NOR gates).  In the real world, this "usable gate" specification doesn't really say much, as it is difficult or even impossible to gauge how many "gates" a design will take up.

As a side note, Xilinx makes one of the industry's largest FPGAs, the XC40250XV.  This chip contains 8464 CLBs (corresponding to ~250000 usable gates, which is probably large enough to implement an entire Pentium-II processor on it).  A single XC40250XV chip can cost upwards of $2000-$3000.

The FPGA in the XS40 board is an 84 pin "plastic leaded chip carrier" (PLCC) version.  You'll notice that the chip is square, and is housed in a brown socket.  Most of the 84 pins on the chip can be used for generic I/O, which means that each pin's function can become anything you want.  For example, this tutorial will be designing and synthesizing a four bit adder, and each of the adder's inputs and outputs can be "routed" to almost any pin on the chip.
 
The XS40 board has more than just the FPGA, however.  It also contains an 8031 microcontroller.  The 8031 is a derivative of Intel's very old (and still very popular) 8051 series of microcontrollers.  It operates at about 12 MHz (although its performance is approximately equal to a 68HC11 running at 1 MHz), and most of its 32 I/O pins are routed to the FPGA.  This means that if want to use the FPGA's generic I/O pins that also happen to be connected to the 8031, we must "disable" the 8031 so that it will not interfere.  Disabling the microcontroller will be explained later.  Note that we will likely never use the 8031 in any EE 411 projects.

Connected to the 8031, and also to the FPGA, is a 32k static RAM chip.  This chip is used to store the code for the 8031.  However, the FPGA can also access this SRAM directly, although this process is a bit complex.  See me if you want/need to use the SRAM in any EE 411 design project.  Note that this RAM chip is volatile, which means that it will be erased when the power is removed.

Another peripheral contained on the XS40 board is a VGA connector!  Using a very simple resistor network, a "crude" D/A converter is set up, making it possible to output Red, Green, and Blue values to a VGA monitor in the proper synchronization (up to 64 colors on the screen).  With this connector, it's possible to create a character generator, make a "paintbrush" style drawing program, display a picture stored in the SRAM chip, etc. right from the XS40 board.  Of course, the process of outputting VGA signals through the FPGA's I/O ports is not easy, but there are some application notes on the XESS website that describe the process.  In addition to the VGA connector, there is also a 7-segment LED contained on the board which allows you to display a single digit number from within your program/hardware.

The other connection on the XS40 board is a parallel port connector.  We use this connector to download bitstreams to the FPGA, as well as program the 32k SRAM chip with 8031 code (if desired).  The program used to download bitstreams to the boards is called XSTOOLS, which is separate from Xilinx Foundation (the download process is described later in this tutorial).

Note that the bitstream that you download to the FPGA is also volatile, which means that the FPGA is erased every time the power is removed.  The XS95 (CPLD) board, however, retains its bitstream indefinitely, but can only be erased/reprogrammed a limited number of times (up to around 10000 write/erase cycles).  The XS40 board can be reprogrammed an unlimited number of times.  If you need the FPGA board to retain its bitstream even when power is removed, note that there is a socket for a ROM on the XS40 board.  You can download the bitstream to this ROM and make it "permanent," but we will not be doing this in EE 411.

At the XESS website you can download schematics, manuals, tutorials, etc. for the XS40 board.  A local copy of the XS40/95 schematic layout is available here.  Note that there are several schematics contained with that pdf file.  We have "version 1.2" of both the XS40 and the XS95 boards, so you should probably print both those pages out your reference (pages 5 and 12 of the pdf file).  Note that the XS40 v1.2 schematic layout shows that the FPGA is an XC4005XL, instead of the XC4010XL that our ECE labs have.  The only difference between those two chips is their internal capacity.  Externally they are equivalent, so just assume that the schematic also applies to the XC4010XL chip.

The website also mentions something called "Xtend" boards.  These are add-on boards that give further peripherals including switches, more LEDs, 16 bit D/A and A/D conversion, a PS/2 keyboard connector, and a prototyping area.  We have been expecting a shipment of these boards for our labs, but they have not come in yet.

After a bitstream has been downloaded to the XS40 board, we need some way to test the design.  We will be using the Switch Register Box (SRB) to input signals to the FPGA, as well as display outputs from within the SRB's LED display.  This is the same SRB used in EE 332, if you recall.  You will also need to print out or bookmark the SRB Pinout so that you can use it for testing your designs.

Creating a Bitstream
 

Now that you know the basics of the XS40 board, we can now create some hardware in Foundation that we can download to the XS40.  For this tutorial we will be creating and synthesizing a 4 bit adder, downloading the adder to the XS40 board, and testing it with the SRB.
 

To begin, go to a workbench that has an XS40 board.  You can tell that it's an XS40 board (and not an XS95 board) by the main chip.  It should read "XC4010XL" somewhere on the chip.  If it says "95108" then it's an XS95 board.  While we could create this design for the XS95 board, it requires some extra steps, so the XS40 boards are used to keep things simple.  The board has been placed onto a breadboard, and note that each pin on the two sides of the board have been numbered (by 5's).  These pins also correspond to the pins on the FPGA chip, as they have been "brought out" to the breadboard.  There should be a parallel port connection to the DB-25 connector, and there should also be a 9V DC power jack connected to the breadboard, although it won't necessarily be "plugged" into the XS40 board.  This plug must be connected into the power jack of the XS40 board before it can be used.

Once you're on a bench with an XS40 board, start Foundation and create a new project.  It is recommended that the project be placed in your M:\ drive because there has been problems with people searching the C:\TEMP directories in each computer, and stealing homework/design solutions.  This tutorial will create approximately 500k of files inside your M:\ drive.  If you must use C:\TEMP, remember to remove the files from there after you're finished (after moving them somewhere else, of course).

Select "XC4000XL" as the chip family, and "4010XLPC84" as the part #.  The "speed" rating does not matter.  I also recommend that you name the project "fpga_add" to reduce confusion.

Create a new schematic file, and add the "ADD4" component to the sheet.  This is a four bit adder.  You can also use the adder you created as one of your first homework assignments, although using the "ADD4" component is easier.

Here is the ADD4 component.  Notice that S = A + B, and the component also has Carry In, Carry Out, and Overflow connections.
 

Next, add IBUF's and OBUF's to each input and output, respectively.  As you recall, these components tell Foundation that the connections to this adder will eventually be routed to the actual pins of the FPGA chip.  We will ignore the Overflow output in this tutorial, so you do not need to connect it to anything.

After you have placed the IBUFs and OBUFs, add input and output terminals according to the picture above.  You can give the terminals different names, but I advise you to keep them the same (it will make things easier later).

Next, connect the wires.

Even though our adder circuit is now "done," there is one extra thing that must be done to the schematic.  Recall that there is an 8031 microcontroller, as well as a 32k SRAM chip, connected to various pins of the FPGA.  We do not want these connections to interfere with our circuit, so we must add few things so that these two chips are "disabled."  To do this, we simply tie the Chip Enable lines of each chip to +Vcc, which tristate the outputs of each chip and allow us freedom to use any I/O pin on the FPGA.

To tie these pins to Vcc, first add a "VCC" component to the schematic.

Next, add two OBUFs and two output terminals (remember to properly name the output terminals), as shown in the above picture.  Connect them with wires, and we're done with the schematic!

Now you can follow the steps that you are familiar with... First you must create the netlist, perform an integrity check, then export the netlist in Edif 200 format (as shown above).  After this, save the schematic and close the schematic capture window.

At this point it is recommended that you perform a functional simulation on the adder, just to make sure things are working.

Now that our schematic is finished, we must now tell Foundation which pin numbers on the actual FPGA we want to use.  Essentially we "assign" pin numbers to each input and output terminal in our schematic.  Once we do this, each input and output terminal will then physically be connected to the corresponding pin on the XS40 board.

There are a number of ways to assign pin numbers, but the easiest way is through the UCF (universal constraint file) file.  To edit the UCF file, double click on the UCF filename contained in project manager, as shown above.

Notice that the UCF file already contains a number of items.  However, as it says, all the lines that start with the "#" or "//" symbols are commented out, which means that the compiler will ignore them.  Scrolling down, notice that the UCF file is already empty except for comments (which outline many of the things you can specify from within the UCF file).

One of the comments in the UCF file is shown above.  You may delete everything in the UCF file except for these lines, which shows you how to specify pin numbers.  Notice the syntax...  "NET" refers to a signal or wire inside your schematic, "SCLINF" is the name of the signal, "LOC" stands for location, and "P125" means pin 125.

The image above shows how to assign pin numbers to each of our I/O terminals in the schematic.  The pin numbers I choose to use were more or less arbitrary.  However, you can't just use any pin you want.  Some of the 84 pins on the FPGA are Vcc, some are ground pins, and some have dedicated special functions.  In addition, some pins are also connected to peripherals on the XS board, such as the parallel port.  Eventually I will create a list of "free" pins that you can always use in a project, but for now it's best to use what I've shown above.  So you don't have to retype the constraints, you can cut and paste this text:

NET CIN LOC  = P81;
NET A0 LOC   = P28;
NET A1 LOC   = P60;
NET A2 LOC   = P58;
NET A3 LOC   = P50;
NET B0 LOC   = P56;
NET B1 LOC   = P51;
NET B2 LOC   = P57;
NET B3 LOC   = P59;
NET SUM0 LOC   = P41;
NET SUM1 LOC   = P40;
NET SUM2 LOC   = P39;
NET SUM3 LOC   = P38;
NET COUT LOC = P35;

NET RESET LOC = P36;
NET CHIPSEL LOC = P65;
 

At this point you might want to get out the schematics for the XS40 board so that you can see the various connections and peripherals connected to the XS board.  Note that "J1" corresponds to the parallel port connections, "J3" are the connections that connect to the breadboard (pin numbers on J3 exactly correspond to pin numbers of the FPGA), etc.  There is also a pin that corresponds to a 12MHz oscillator.  Certain designs in EE411 may require a clock, so connecting this pin from within schematic capture (as an input terminal) will give you a 12 MHz clock.  You can divide this clock with a clock-divider component if you need a slower clock.

After you've finished with the UCF file, save and close it.

Our design is now ready to be synthesized into a bitstream.  To synthesize, click on "implement".  This will invoke the Xilinx Design Manager.

From within design manager, click on Design|Implement.

Click on Options.

While we won't specifically use it in this tutorial, you should click on "produce timing simulation data."  Clicking this option will give real-world timing data on how the FPGA will actually perform, i.e. how fast it can run.  We will show how to use this timing data later.

After this, click on "Edit Template" (to the right of "Implementation").

In this "Edit Template" window, click on the "interface" tab.  Under simulation data options, select "VHDL" as the format.

After Foundation has produced the bitstream, it will generate VHDL code that will exactly represent the finished bitstream.  Later, we can open this VHDL code from within Active VHDL and perform timing-accurate simulations of the FPGA.

After this, go back to the "implement" window and click on Run.  This will invoke the "Flow Engine" which will perform the steps necessary to create the bitstream.  Most of the actual "synthesis" occurs in the Flow Engine, and for complex designs this step can take many hours (although our 4 bit adder should only take a minute or so).  Note that there are many things that can go wrong from within Flow Engine, i.e. design errors, crashes, etc.  Just be patient.  If you followed the above steps exactly, it's unlikely that you will get any errors.

The Flow Engine is simply a script that invokes a bunch of command-line synthesis tools.  In theory, you could compile and synthesize your entire design using an MSDOS prompt.  Don't worry if you don't understand what is happening in the above steps, it's beyond the scope of EE 411.

When everything is done, you will see a "Implemented, OK" message next to your design.  If you see a "Implemented, ERRORS", then something went wrong.  You can view the log file to see exactly what went wrong, and attempt to correct the problem.  The most common type of error is a misnamed pin or entry in the UCF file.

At this point you can go to "Tools | EPIC Design Editor" if you want.  The EPIC Design Editor actually shows you what the inside of your chip now looks like, including the wires that have been routed, the CLBs you have used, etc.  Be patient, it can take quite a while to load (at first I thought the program had crashed, but a couple minutes later it showed up!).  EPIC actually allows you to physically route/unroute connections, add functions, etc., but this capability is far beyond what we'll be using in EE 411.  For right now it's just "neat" to see what your design looks like.  To zoom in/out of your design, right click and shift-right-click (you can pan around the design by holding down the right mouse button as well).  Also, check and uncheck various items in the "layer visibility" box to see what happens!
 

Downloading to the XS40 Board
 

If you look inside your project directory, you will see a file called "fpga_add.bit".  This is the file that will be downloaded to the XS40 board.  Copy this file to the root directory of your M: drive, i.e. M:\.  This will make things easier.

Before you download to the XS40 board, make sure that the parallel port connector is properly connected to the XS40 board.  Also make sure that the power supply is plugged into the XS40 board.  When it's plugged in, the 7 segment LED display on the board should be very faintly lit.  If it's not lit at all, then something may be wrong.

Open up an MSDOS command prompt, and change directories to C:\XSTOOLS\BIN.  "Xstools" is the program supplied by XESS corporation to download files to their boards.  To download "fpga_add.bit" to the XS40 board, simply type in the following:

This will invoke the program XSLOAD and download the bitstream.  "xess" is actually an MSDOS batch file which automatically selects LPT2 as our parallel port address, but you don't need to worry about that.  If "xess.bat" is missing, you can execute XSLOAD directly with the following syntax:

XSLOAD -p 2 fpga_add.bit

After you execute XSLOAD, the program should download the file into the XS40 board.  Note that XSLOAD is rather "dumb" program, and it will download to the board even if it's not connected!  There is no feedback mechanism that shows that the bitstream was properly downloaded.  However, during download, the 7 segment LED should momentarily flash on and off, perhaps showing a number or character.  If there seems to be zero activity on the LEDs during download, something may be wrong.

Note that unplugging the 9V power supply from the XS40 board will erase the bitstream in the FPGA.  You must redownload the bitstream each time power is removed.

Testing the Adder
 

When the bitstream was created by the Flow Engine, two other files were created:  "time_sim.vhd" and "time_sim.sdf".  You can open these two files in Aldec Active-VHDL (the .sdf file lists the various timing parameters of the vhdl netlist, in "standard delay format") and perform a timing-accurate simulation of your circuit.  For this week you won't be required to do this, however.

We can now wire up the XS40 board to the SRB so that we can test the 4 bit adder.  First, go find some red and black bannana-plug cables and connect the SRB to the bench power supply (+5V and ground).  The power connections on the SRB are located on the other side of the toggle switches.  Don't turn on the bench power supply just yet.

Attach the SRB header connector to the protoboard that the XS40 is on.  Notice that pin "1" corresponds to the little triangle on the plastic header.  You'll notice that the SRB pinout (see the start of this tutorial for the pinout) has a number of different connections.  There are switches, outputs, clocks, grounds, etc.  We will be using the even pins 2 through 16 (the "Switch x" pins), and the even pins 20 through 34 (the "output x" pins).  The "switch" pins SW0 through SW7 are the outputs of the 8 toggle switches on the SRB.  The "output" pins O0 through O7 feed the 8 LED's contained within the SRB.  We will use the 8 switches to drive A and B, and 5 LED's to see the SUM plus COUT.

Wire up the XS40 board to the SRB as follows:
 
 

Note:  Connect the carry in to the ground/VCC line of the XESS board, not the SRB. Apparently, using the SRB's ground pin gives erratic results (remember, the ground of the SRB and the ground of the XS boards are different!).  The ground pin of the XS40 board is pin 52, and the VCC pin of the XS40 board is pin 2.

After you have wired the circuit up, turn on the bench power supply (which supplies the SRB) and test it!  If the circuit is not working at all, or is giving erratic results (such as rapidly flashing LEDs or something), then try to re-download the bitstream to the FPGA.  With the above pin connections, you do not have to disconnect the SRB or the bench power supply to redownload, it should still re-download properly.  If that still doesn't work, attempt to trace back some steps to see if something may be wrong (e.g. you're using an XS95 board instead of an XS40, wiring errors, the XS40's 7-segment display isn't dimly lit when power is first applied [which may indicate a bad XS40 board], etc.).

Flipping the 8 toggle switches on the SRB should give you the correct sum on the LEDs.  The first four toggle switches are the 'A' inputs, and the last four are the 'B' inputs.  Note that the 5th LED (corresponding to SRB pin #28) is the carry out, so your answer is a 5 bit sum.  Test many values of inputs and see if you get what you expected!  Pin 81 on the XS40 is the carry in.  You can tie this to VCC or ground depending on if you want a carry-in of 1 or 0, respectively.  Note that you may eventually have to demonstrate to Dr. Rover or myself that your bitstream works, so no cheating :).  As always, if you need help, contact me via email or come to my office hours (Wednesdays, 3-5:00pm).

Remember to properly clean up the bench area after you're finished, including various wires, papers, etc.  Also, remember to unplug the XS40 power supply when it's not in use, and don't leave any files in C:\TEMP that others can steal!

Using the XS95 CPLD Board

The above tutorial focused on the XS40 FPGA board.  However, most of the above steps also apply to using the XS95 CPLD board.  This section outlines what must be done differently to implement the 4-bit adder on the XS95.

• First, you must start the design with chip family XC9500 and part # 95108PC84.  The XC9500 is Xilinx's primary line of CPLD chips.  Typically you cannot implement extremely extremely large designs on CPLDs.  CPLDs are generally better suited for extremely fast combinational networks, and fast state machines.  However, the XS95 board will still be large enough for most designs in EE 411.
• Until you reach synthesis, everything you did for the FPGA is the same for the CPLD.
• When synthesizing in the Flow Engine, some of the menu options change slightly.  You can ignore most of these changes.
• After the Flow Engine finishes, you must perform some extra steps to obtain the bitstream.  XSTOOLS does not use a ".BIT" file like it does for FPGAs, but rather it uses an "SVF" file.  To create the SVF file after Flow Engine is complete, go to Tools|JTAG Programmer, then Output|Create SVF File, save the SVF file to the default directory it gives you, then finally go to Operations|Program (then execute the command).  These steps will create an SVF file that is around 900 KB, you can find it in your project directory.  If the SVF file is very small, i.e. under 20k, then something probably went wrong.  Now you can execute XSLOAD with this SVF file instead of an fpga BIT file.
• Notice that most every pin number changes when moving to the XS95 board.  This means that you can no longer use the above list of pin #'s used for the XS40 board.  I am currently compiling a list of pins that you can freely use on both the XS40 and the XS95 boards.
• Also remember that the bitstream that you download to the XS95 will not be erased when the power is removed.